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[Other] fpga-jpeg

Description: vhdl实现的ＪＰＥＧ嘿嘿 嘿嘿圆圆嘿嘿另-VHDL achieve JPEG laughter laughter another round laughter
Platform: | Size: 103977 | Author: window | Hits:

[Other resource] fpga-jpeg-verilog

Description: fpga-jpeg-verilog在fpga平台使用verilog语言进行jpeg算法实现
Platform: | Size: 104245 | Author: yang | Hits:

[Software Engineering] huawei

Description: 华为FPGA设计流程指南，FPGA设计者、项目管理者必读的文档，看看别人是怎么做的。-Huawei FPGA design flow guide, FPGA designers, project managers must-read documents, take a look at how others do.
Platform: | Size: 31744 | Author: 贺雷 | Hits:

[Compress-Decompress algrithms] MPEG4

Description: 这是一个关于MPEG视频的标准解码程序，其中内容丰富，对想要做视频的同学很有帮助。-It is a standard MPEG video decoding process, which is rich in content, the students want to do video helpful.
Platform: | Size: 131072 | Author: wuwenquan | Hits:

[VHDL-FPGA-Verilog] DCT_IDCT

Description: 离散余弦变换及反离散余弦变换的HDL代码及测试文件。包括VHDL及Verilog版本。可用途JPEG及MEPG压缩算法。-Discrete cosine transform and inverse discrete cosine transform of the HDL code and test files. Including VHDL and Verilog versions. And MEPG can use JPEG compression algorithm.
Platform: | Size: 29696 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] huffman

Description: 用于FPGA的huffman算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-The huffman algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Platform: | Size: 10240 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] quant

Description: 用于FPGA的量化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Quantitative algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Platform: | Size: 14336 | Author: caesar | Hits:

[Picture Viewer] JPEGactFPGA

Description: 利用FPGA实现JPEG算法的研究与实现，研究生的论文，很有参考价值-JPEG algorithm using FPGA realization of Research and Implementation of, post-graduate thesis, a good reference
Platform: | Size: 2592768 | Author: 刘小春 | Hits:

[VHDL-FPGA-Verilog] jpeg.tar

Description: This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288). Image resolution is not limited. It takes an RGB input (row-wise) and outputs to a memory the compressed JPEG image. Its quality is comparable to software solutions.
Platform: | Size: 3416064 | Author: Bill Guan | Hits:

[Other] JPEGimageCompressiontechniquesimplementationandopt

Description: 摘　要 文章以空间监控系统为背景,深入研究了JPEG图像压缩标准的实现方法,并基于FPGA对其进行了实现和优化。文中给出了详细的实现方法和优化过程,测试表明达到了很好的效果。 简单介绍了有损静态图像压缩当前有两种比较流行的标准JPEG和JPEG2000。说明了用JPEG方法压缩的原因。 介绍JPEG基本原理：JPEG对灰度图像的压缩处理过程主要包括:图像分割,离散余弦变换(DCT),量化(Quantization),“Z”形排序(Zigzag Scan),差分脉冲编码调制(Differential Pulse Code Modulation,DPCM)对直流系数(DC),行程长度编码(Run-Length Encoding,RLE)对交流系数(AC),霍夫曼(Huffman)编码等。 JPEG标准的特点是离散余弦变换。 比较详细介绍压缩系统的构成和实现。实现提及步骤， JPEG压缩模块设计和编码模块实现细节。 -Abstract Article in the space monitoring system for the background, in-depth study of the JPEG image compression standard implementation methods and carried out based on FPGA implementation and optimization. In this paper, a detailed method of implementation and optimization of the process, testing showed that to achieve good results. Easy introduction of harmful static image compression has two kinds of comparisons that the current popular standard JPEG and JPEG2000. Illustrated by the reasons for JPEG compression method. JPEG introduce the basic principles: JPEG compression of gray-scale image processing include: image segmentation, discrete cosine transform (DCT), quantization (Quantization), "Z"-shaped sort (Zigzag Scan), differential pulse code modulation (Differential Pulse Code Modulation, DPCM) on the DC coefficient (DC), Run Length Encoding (Run-Length Encoding, RLE) of the exchange coefficient (AC), Hoffman (Huffman) coding. JPEG standard is characterized by discrete
Platform: | Size: 523264 | Author: 压子 | Hits:

[VHDL-FPGA-Verilog] Mars_EP1C6F_Fundermental_demo(Verilog)

Description: FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。-FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and multiplier, such as MUX.
Platform: | Size: 1244160 | Author: chenlu | Hits:

[VHDL-FPGA-Verilog] jpegVerilog

Description: FPGA实现jpeg Verilog源代码-FPGA realization of jpeg Verilog source code
Platform: | Size: 104448 | Author: 许伟 | Hits:

[Special Effects] ejpgl

Description: 嵌入JPEG编解码器图书馆 一个开源JPEG为嵌入系统优先编解码器包，包括编码器和译码器。 协定，优选为具体硬件，容易被端起到各种各样的嵌入OS， 类似Handel-C的ESL工具、多处理机系统和FPGA。 -Embedded JPEG Codec Library An open source JPEG codec library optimized for embedded system, including both encoder and decoder. Compact, optimized for specific hardware, easy to be ported to various embedded OS, ESL tools like Handel-C, multi-processor systems and FPGA.
Platform: | Size: 163840 | Author: LXP | Hits:

[Picture Viewer] 81404621JPEG-DCT

Description: 基于FPGA的DCT实现源代码,已通过MODELSIM验证。-FPGA based source code of DCT
Platform: | Size: 1024 | Author: 宋建 | Hits:

[VHDL-FPGA-Verilog] fpga_jpeg

Description: 图像jpeg压缩算法,用verilog HDL在FPGA上的实现 -Jpeg image compression algorithm, using verilog HDL Implementation in FPGA
Platform: | Size: 103424 | Author: 沧海一笑 | Hits:

[Embeded-SCM Develop] Pelmanism.tar

Description: FPGA reading JPEG pictures from SD card
Platform: | Size: 4057088 | Author: lo | Hits:

[VHDL-FPGA-Verilog] VERILOG-jpeg

Description: 用Verilog语言在FPGA上实现JPEG图片的解码，附带testbench-With the Verilog language in the FPGA to achieve JPEG image decoding, with testbench
Platform: | Size: 103424 | Author: ken | Hits:

[Compress-Decompress algrithms] JPEG-LS

Description: 基于改进JPEG-LS算法的遥感图像近无损压缩专利，由航天五院508所申报，很详细的介绍了算法和fpga的实现-Improved JPEG-LS algorithm near lossless compression patent, the space the five branches of 508 reporting, a detailed explanation of the algorithm and implementation fpga
Platform: | Size: 673792 | Author: 小化 | Hits:

[Compress-Decompress algrithms] JPEG-2000-master

Description: jpeg code for imag ecompresison using python or java code
Platform: | Size: 939008 | Author: arteja | Hits:

[VHDL-FPGA-Verilog] FPGA实现Jpeg压缩，和视频采集程序

Description: FPGA实现Jpeg压缩，和视频采集程序(Zynq - Main - register access Mio)
Platform: | Size: 103424 | Author: kongqiweiliang | Hits:
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